| Laboratory practises |
Basic signal processing systems will be implemented using FPGAs.
CG6, CG9, CE39, CE45 and CG13 competencies will be worked on. |
| Projects |
Working groups of two or more students will be established. Each group will develop two projects along the course. These projects will address the design of signal processing systems of low and medium complexity, respectively.
Additionally, small groups (Groups Type C) will be available allowing monitoring the projects to be developed in the course. Activities to be developed in groups C:
Activity 1.
Description, analysis and discussion of the systems designed in the first project of the course. Presentation of results. Duscussion of design alternatives.
Activity 2.
Analysis and monitoring of the proposed solution for the second project.
Activity 3.
Demonstration of the behavior of systems designed in the second project. Analysis and discussion of results.
CG6, CG9, CE39, C345, CG13, CT2, CG4 and CT4 competencies will be worked on. |
| Master Session |
The theoretical content of the course and the introductory activities of both the theoretical and practical contents will be presented.
CG6, CE39 and CE45 competencies will be worked on. |
